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ASAHI KASEI
[AKD4122]
AKD4122
Evaluation board Rev.A for AK4122
GENERAL DESCRIPTION The AKD4122 is an evaluation board for the digital sample rate converter, the AK4122 with built-in digital audio interface receiver (DIR). The AKD4122 has the digital audio interface and can achieve the interface with digital audio system via opt-connector. n Ordering guide
AKD4122 --Evaluation board for AK4122 (Cable for connecting with printer port of IBM-AT compatible PC and control software are packed with this. This control software does not operate on Windows NT.)
FUNCTION * DIR/DIT with optical input/output * 10pin Header for AKM AD/DA evaluation board * BNC connector for an external clock input * 10pin Header for serial control mode
AVDD, DVDD Opt In AK4114 AGND, DGND AK4114 Opt Out
DSP Data
10pin Header
10pin Header
DSP Data
AK4122
BICK In Clock Divider MCLK In
Digital In
10pin Header Opt In
Control Data
MCLK In
Clock Divider
10pin Header DSP Data
AK4114
Opt In Opt Out
Figure 1. AKD4122 Block Diagram * Circuit diagram and PCB layout are attached at the end of this manual.
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2003/06
ASAHI KASEI
[AKD4122]
1. Evaluation Board Manual n Operation sequence
1) Set up the power supply lines. [AVDD] (red) = 3.0 3.6V (typ. 3.3V, AVDD pin) [DVDD] (red) = 3.0 3.6V (typ. 3.3V, DVDD pin) [+5V] (orange) = +5V (for regulator) [VCC] (blue) = 3.0 3.6V (typ. 3.3V, for digital logic) [AGND] (black) = 0V [DGND] (black) = 0V Each supply line should be distributed from the power supply unit. 2) Set up the evaluation mode, jumper pins. (See the followings.) 3) Power on. The AK4122 should be reset once bringing SW6 (PDN) "L" upon power-up.
n Evaluation mode
I/O ports and jumper pins on the board should be set according to the following explanation in order to evaluate each pass of the AK4122. The block diagram is shown in Figure 2.
MCKO RX1 RX2 RX3 RX4
RX1 RX2 RX3 RX4 OPS1-0 TX
INT0 INT1 INT2
R
FILT
TX PDN
IPS1-0
DIR PORT3 De-em Filter
OSEL
SMUTE Serial Audio I/F
LRCK BICK SDTO
PORT1 BICK1 LRCK1 SDTI
BICK1 LRCK1 SDTI
Serial Audio I/F PORT2
SRC
BYPS
ISEL1-0
LRCK BICK SDTO OMCLK
PLL
BICK2 LRCK2 SDTIO MCLK2
BICK2 LRCK2 SDTIO
Serial Audio I/F Control Register
M/S2 M/S3 MCKE
AVDD AVSS
DVDD DVSS
CDTO CDTI CCLK CSN
Figure 2. AK4122 Block Diagram
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2003/06
ASAHI KASEI
[AKD4122]
(1) AK4122 PORT1 SRC AK4122 PORT3 Refer to page 5 for input port setting, and page 15 18 for output port setting.
PORT4 DIR1 U12 AK4114 U14 AK4114 PORT10 DIT3
AK4122
BICK BICK1 PORT5 DSP1 LRCK LRCK1 SDTO SDTI OMCLK PORT9 DSP3
J4 EXT1
Divider
J3 EXT3
Figure 3. AK4122 PORT1 SRC AK4122 PORT3 (2) AK4122 PORT2 SRC AK4122 PORT3 Refer to page 6 9 for input port setting, and page 15 18 for output port setting.
PORT6 DIR2 U13 AK4114 U14 AK4114 PORT10 DIT3
AK4122
BICK2 PORT7 DSP2 LRCK2 SDTIO MCLK2 J2 EXT2 Divider Divider J3 EXT3 BICK LRCK SDTO OMCLK PORT9 DSP3
Figure 4. AK4122 PORT2 SRC AK4122 PORT3 (3) AK4122 DIR SRC AK4122 PORT3 Refer to page 10 for input port setting, and page 15 18 for output port setting.
PORT10 U14 AK4114 DIT3
AK4122
PORT3 DIR RX2 RX3 J1 RX RX4 LRCK SDTO OMCLK PORT9 DSP3 RX1 BICK
Divider
J3 EXT3
Figure 5. AK4122 DIR SRC AK4122 PORT3
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2003/06
ASAHI KASEI
[AKD4122]
(4) AK4122 PORT1 SRC AK4122PORT2 Refer to page 5 for input port setting, and page 11 14 for output port setting.
PORT4 DIR1 U12 AK4114 U13 AK4114 PORT8 DIT2
AK4122
BICK2 BICK1 PORT5 DSP1 LRCK2 LRCK1 SDTIO SDTI MCLK2 PORT7 DSP2
J4 EXT1
Divider
J2 EXT2
Figure 6. AK4122 PORT1 SRC AK4122 PORT2 (5) AK4122 DIR SRC AK4122 PORT2 Refer to page 10 for input port setting, and page 11 14 for output port setting.
PORT8 U13 AK4114 DIT2
AK4122
PORT3 DIR RX2 RX3 J1 RX RX4 LRCK2 SDTIO MCLK2 PORT7 DSP2 RX1 BICK2
Divider
J2 EXT2
Figure 7. AK4122 DIR SRC KA4122 PORT2 (6) Bypass Mode Refer to page 5 10 for input port setting, and output port setting should be master mode. The bypass mode of the AK4122 is set by the register. In bypass mode, the DIT function of the AK4114 can not be used as the output port. 10pin PORT should be used instead. Input BICK, LRCK, and DATA are output from the output port side in the bypass mode.
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2003/06
ASAHI KASEI
[AKD4122]
(1) Setting for Input port (AK4122 PORT1) (1-1) Slave Mode 1. When using DIR function of AK4114 (U12) When using PORT4 (DIR1), nothing should be connected to J4 (EXT1) and PORT5 (DSP1). JP12 (EXT1) should be short. JP11 BICK1 JP12 EXT1 JP13 SDTO JP14 LRCK1
DIR
EXT
* SW2 setting (See Table 1, 2) Upper-side is "H" and lower-side is "L". SW2 No. 1 2 3 4 Name OCKS DIF0 DIF1 DIF2 ON ("H") Fixed to "L" AK4114 Audio Format Setting Refer to Table 2 Table 1. SW2 setting Mode 0 1 2 3 AK4114 AK4122 DIF2 DIF1 DIF0 DIF1 DIF0 16bit, LSB justified 0 0 0 0 0 24bit, MSB justified 1 0 0 0 1 24bit, I2S Compatible 1 0 1 1 0 24bit, LSB justified 0 1 1 1 1 Table 2. AK4114 Audio interface format setting Audio I/F Format OFF ("L")
Default
* DIF1-0 of the AK4122 is set by the register. 2. When connecting with the serial interface of UPD, ROHDE & SCHWARZ When using PORT5 (DSP1), nothing should be connected to PORT4 (DIR1). BICK is input from J4 (EXT1), and the LRCK and SDTI are supplied from UPD. JP12 (EXT1) should be open. JP11 BICK1 JP12 EXT1 JP13 SDTO JP14 LRCK1
DIR
EXT
3. All clocks are fed through the 10pin port When using PORT5 (DSP1), nothing should be connected to J4 (EXT1) and PORT4 (DIR1). JP12 (EXT1) should be short. JP11 BICK1 JP12 EXT1 JP13 SDTO JP14 LRCK1
DIR
EXT
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2003/06
ASAHI KASEI
[AKD4122]
(2) Setting for Input port (AK4122 PORT2) (2-1) Slave mode 1. When using DIR function of AK4114 (U13) When using PORT6 (DIR2), nothing should be connected to J2 (EXT2) and PORT7 (DSP2). Set JP18 (MCLK2) to the "DIR" when MCLK is supplied to the AK4122. JP15 SDTIO JP16 BICK2 JP17 LRCK2 JP18 MCLK2
DIR * SW3 setting (See Table 3, 4, 5) Upper-side is "H" and lower-side is "L". SW3 No. 1 2 3 4 Name OCKS DIF0 DIF1 DIF2
EXT
DIR
EXT
DIR
EXT
ON ("H") OFF ("L") AK4114 Master Clock Output Setting Refer to Table 4 AK4114 Audio Format Setting Refer to Table 5 Table 3. SW3 setting
Mode 0 1
OCKS 0 1
MCKO1 X'tal fs 256fs 256fs 96kHz 512fs 512fs 48kHz Table 4. AK4114 MCKO1 setting
Default
Mode 0 1 2 3
AK4114 AK4122 DIF2 DIF1 DIF0 IDIF1 IDIF0 16bit, LSB justified 0 0 0 0 0 24bit, MSB justified 1 0 0 0 1 24bit, I2S Compatible 1 0 1 1 0 24bit, LSB justified 0 1 1 1 1 Table 5. AK4114 Audio interface format setting Audio I/F Format
Default
* IDIF1-0 of the AK4122 is set by the register.
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2003/06
ASAHI KASEI
[AKD4122]
2. When connecting with the serial interface of UPD, ROHDE & SCHWARZ When using PORT7 (DSP2), nothing should be connected to PORT6 (DIR2). MCLK is input from J2 (EXT2), BICK is supplied by using the clock dividing circuit on this evaluation board and the LRCK and SDTI are supplied from UPD. Set JP18 (MCLK2) to the "EXT" when MCLK is supplied to the AK4122. JP15 SDTIO JP16 BICK2 JP17 LRCK2 JP18 MCLK2
DIR
EXT
DIR
EXT
DIR
EXT
* Clock Setting MCLK is input from J2 (EXT2), BICK is supplied by using the clock dividing circuit. JP4 (DIV2) and JP5 (CLK2) are set by referring to Table 6. JP6 (BCFS) selects the frequency of BICK. JP7 (EXT2) should be open. JP4 DIV2 JP5 CLK2 JP6 BCFS JP7 EXT2
256 256 512 768
384
64fs
32fs
fs 8kHz
32kHz
44.1kHz
48kHz
88.2kHz 96kHz
MCLK JP4(DIV2) 256fs = 2.048MHz 256 384fs = 3.072MHz Open 512fs = 4.096MHz 512 768fs = 6.144MHz 768 256fs = 8.192MHz 256 384fs = 12.288MHz Open 512fs = 16.384MHz 512 768fs = 24.576MHz 768 256fs = 11.2896MHz 256 384fs = 16.9344MHz Open 512fs = 22.5792MHz 512 768fs = 33.8688MHz 768 256fs = 12.288MHz 256 384fs = 18.432MHz Open 512fs = 24.576MHz 512 768fs = 36.864MHz 768 256fs = 22.5792MHz 256 384fs = 33.8688MHz Open 256fs = 24.576MHz 256 384fs = 36.864MHz Open Table 6. Example for Clock setting
JP5(CLK2) 256 384 256 256 256 384 256 256 256 384 256 256 256 384 256 256 256 384 256 384
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2003/06
ASAHI KASEI
[AKD4122]
3. All clocks are fed through the 10pin port When using PORT7 (DSP2), nothing should be connected to J2 (EXT2) and PORT6 (DIR2). JP7 (EXT2) should be short. JP15 SDTIO JP16 BICK2 JP17 LRCK2 JP18 MCLK2
DIR (2-2) Master mode MCLK must be provided in the master mode.
EXT
DIR
EXT
DIR
EXT
1. When using DIR function of AK4114 (U13) When using PORT6 (DIR2), nothing should be connected to J2 (EXT2) and PORT7 (DSP2). Set JP18 (MCLK2) to the "DIR" in order to supply MCLK to the AK4122. JP15 SDTIO JP16 BICK2 JP17 LRCK2 JP18 MCLK2
DIR * SW3 setting (See Table 7, 8, 9) Upper-side is "H" and lower-side is "L". SW3 No. 1 2 3 4 Name OCKS DIF0 DIF1 DIF2
EXT
DIR
EXT
DIR
EXT
ON ("H") OFF ("L") AK4114 Master Clock Output Setting Refer to Table 8 AK4114 Audio Format Setting Refer to Table 9 Table 7. SW3 setting
Mode 0 1
OCKS MCKO1 X'tal 0 256fs 256fs 1 512fs 512fs Table 8. AK4114 MCKO1 setting
fs 96kHz 48kHz
Mode 0 1
AK4114 AK4122 DIF2 DIF1 DIF0 IDIF1 IDIF0 24bit, MSB justified 1 1 0 0 1 24bit, I2S Compatible 1 1 1 1 0 Table 9. AK4114 Audio interface format setting Audio I/F Format
* IDIF1-0 of the AK4122 is set by the register.
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2003/06
ASAHI KASEI
[AKD4122]
2. All clocks are fed through the 10pin port When using PORT7 (DSP2), nothing should be connected to J2 (EXT2) and PORT6 (DIR2). JP7 (EXT2) should be short. MCLK is supplied to the AK4122, and the DATA that synchronizes with BICK and LRCK output from the AK4122 is supplied to the AK4122. JP15 SDTIO JP16 BICK2 JP17 LRCK2 JP18 MCLK2
DIR (2-3) SW1 setting
EXT
DIR
EXT
DIR
EXT
Set SW1 according to the mode of the AK4122 PORT2. SW1 No. 1 2 3 Name M/S2 M/S3 TST4 ON ("H") OFF ("L") Master Mode Slave Mode Master Mode Slave Mode Fixed to "L" Table 10. SW1 setting Default L L L
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2003/06
ASAHI KASEI
[AKD4122]
(3) Setting for Input port (AK4122 DIR) (3-1) Setting for DIR input The signal source of AK4122's DIR can be set by JP2 (RX) and JP3 (RX1-4).
VCC L1 47u PORT3
VCC GND OUT
3 2 1
C6 0.1u OPT R24 470 JP3 JP2 RX RX1 RX2 RX3 RX4 RX1 RX2 RX3 RX4
DIR
J1 RX R25 75 C11 0.1u BNC
RX1-4
Figure 8. DIR input circuit
JP2 RX JP2 RX
RX BNC RX BNC Optical Coaxial Figure 9. JP2 setting JP3 RX1-4 RX1 RX2 RX3 RX4 RX1 JP3 RX1-4 RX1 RX2 RX3 RX4 RX2 RX3 Figure 10. JP3 setting JP3 RX1-4 RX1 RX2 RX3 RX4 RX4 JP3 RX1-4 RX1 RX2 RX3 RX4
(3-2) Setting for DIR through signal DIR through signal of the AK4122 is output to TX pin via PORT2 (TX).
VCC TX C1 0.1u
3 2 1
PORT2
IN VCC GND
TX
Figure 11. DIR through signal
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2003/06
ASAHI KASEI
[AKD4122]
(4) Setting for Output port (AK4122 PORT2) (4-1) Slave mode 1. When using DIT function of AK4114 (U13) When using X'tal (X1) and PORT8 (DIT2), nothing should be connected to PORT6 (DIR2) and PORT7 (DSP2). Set JP18 (MCLK2) to the "DIR" when MCLK is supplied to the AK4122. When MCLK frequency is changed, the value of X'tal (X1) frequency should be changed according to MCLK frequency. JP15 SDTIO JP16 BICK2 JP17 LRCK2 JP18 MCLK2
DIR * SW3 setting (See Table 11, 12, 13) Upper-side is "H" and lower-side is "L". SW3 No. 1 2 3 4 Name OCKS DIF0 DIF1 DIF2
EXT
DIR
EXT
DIR
EXT
ON ("H") OFF ("L") AK4114 Master Clock Output Setting Refer to Table 12 AK4114 Audio Format Setting Refer to Table 13 Table 11. SW3 setting
Mode 0 1
OCKS 0 1
MCKO1 X'tal fs 256fs 256fs 96kHz 512fs 512fs 48kHz Table 12. AK4114 MCKO1 setting
Default
Mode 0 1 2 3
AK4114 AK4122 DIF2 DIF1 DIF0 IDIF1 IDIF0 24bit, MSB justified 1 0 0 0 0 24bit, MSB justified 1 0 0 0 1 24bit, I2S Compatible 1 0 1 1 0 24bit, MSB justified 1 0 0 1 1 Table 13. AK4114 Audio interface format setting Audio I/F Format
Default
* IDIF1-0 of the AK4122 is set by the register.
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2003/06
ASAHI KASEI
[AKD4122]
2. When connecting with the serial interface of UPD, ROHDE & SCHWARZ When using PORT7 (DSP2), nothing should be connected to PORT6 (DIR2). MCLK is input from J2 (EXT2), BICK and LRCK are supplied by using the clock dividing circuit on this evaluation board to the AK4122. Set JP18 (MCLK2) to the "EXT" when MCLK is supplied to the AK4122. JP15 SDTIO JP16 BICK2 JP17 LRCK2 JP18 MCLK2
DIR
EXT
DIR
EXT
DIR
EXT
* Clock Setting MCLK is input from J2 (EXT2), BICK and LRCK are generated by using the clock dividing circuit. JP4 (DIV2) and JP5 (CLK2) are set by referring to Table 14. JP6 (BCFS) selects the frequency of BICK. JP7 (EXT2) should be open. JP4 DIV2 JP5 CLK2 JP6 BCFS JP7 EXT2
256 256 512 768
384
64fs
32fs
fs 32kHz
44.1kHz
48kHz
88.2kHz 96kHz
MCLK JP4(DIV2) JP5(CLK2) 256fs = 8.192MHz 256 256 384fs = 12.288MHz Open 384 512fs = 16.384MHz 512 256 768fs = 24.576MHz 768 256 256fs = 11.2896MHz 256 256 384fs = 16.9344MHz Open 384 512fs = 22.5792MHz 512 256 768fs = 33.8688MHz 768 256 256fs = 12.288MHz 256 256 384fs = 18.432MHz Open 384 512fs = 24.576MHz 512 256 768fs = 36.864MHz 768 256 256fs = 22.5792MHz 256 256 384fs = 33.8688MHz Open 384 256fs = 24.576MHz 256 256 384fs = 36.864MHz Open 384 Table 14. Example for Clock setting
3. All clocks are fed through the 10pin port When using PORT7 (DSP2), nothing should be connected to J2 (EXT2) and PORT6 (DIR2). JP7 (EXT2) should be short. JP15 SDTIO JP16 BICK2 JP17 LRCK2 JP18 MCLK2
DIR
EXT
DIR
EXT
DIR
EXT
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2003/06
ASAHI KASEI
[AKD4122]
(4-2) Master mode MCLK must be provided in the master mode. 1. When using DIT function of AK4114 (U13) When using X'tal (X1) and PORT8 (DIT2), nothing should be connected to PORT6 (DIR2) and PORT7 (DSP2). Set JP18 (MCLK2) to the "DIR" when MCLK is supplied to the AK4122. When MCLK frequency is changed, the value of X'tal (X1) frequency should be changed according to MCLK frequency. JP15 SDTIO JP16 BICK2 JP17 LRCK2 JP18 MCLK2
DIR * SW3 setting (See Table 15, 16, 17) Upper-side is "H" and lower-side is "L". SW3 No. 1 2 3 4 Name OCKS DIF0 DIF1 DIF2
EXT
DIR
EXT
DIR
EXT
ON ("H") OFF ("L") AK4114 Master Clock Output Setting Refer to Table 16 AK4114 Audio Format Setting Refer to Table 17 Table 15. SW3 setting
Mode 0 1
OCKS MCKO1 X'tal fs 0 256fs 256fs 96kHz 1 512fs 512fs 48kHz Table 16. AK4114 MCKO1 setting
Mode 0 1
AK4114 AK4122 DIF2 DIF1 DIF0 IDIF1 IDIF0 24bit, MSB justified 1 1 0 0 1 24bit, I2S Compatible 1 1 1 1 0 Table 17. AK4114 Audio interface format setting Audio I/F Format
* IDIF1-0 of the AK4122 is set by the register.
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2003/06
ASAHI KASEI
[AKD4122]
2. When connecting with the serial interface of UPD, ROHDE & SCHWARZ When using PORT7 (DSP2), nothing should be connected to PORT6 (DIR2) and PORT8 (DIT2). MCLK is input from J2 (EXT2), BICK LRCK, and DATA are supplied from the AK4122. Set JP18 (MCLK2) to the "EXT" in order to supply MCLK to the AK4122. JP15 SDTIO JP16 BICK2 JP17 LRCK2 JP18 MCLK2
DIR
EXT
DIR
EXT
DIR
EXT
* Clock Setting MCLK is input from J2 (EXT2). JP7 (EXT2) should be open. JP4 DIV2 JP5 CLK2 JP6 BCFS JP7 EXT2
256 256 512 768
384
64fs
32fs
3. All clocks are fed through the 10pin port When using PORT7 (DSP2), nothing should be connected to J2 (EXT2), PORT6 (DIR2) and PORT8 (DIT2). JP7 (EXT2) should be short. MCLK is supplied to the AK4122, and BICK, LRCK and DATA are supplied from the AK4122. JP15 SDTIO JP16 BICK2 JP17 LRCK2 JP18 MCLK2
DIR (4-3) SW1 setting
EXT
DIR
EXT
DIR
EXT
Set SW1 according to the mode of the AK4122 PORT2. SW1 No. 1 2 3 Name M/S2 M/S3 TST4 ON ("H") OFF ("L") Master Mode Slave Mode Master Mode Slave Mode Fixed to "L" Table 18. SW1 setting Default L L L
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2003/06
ASAHI KASEI
[AKD4122]
(5) Setting for Output port (AK4122 PORT3) (5-1) Slave mode 1. When using DIT function of AK4114 (U14) When using X'tal (X2) and PORT10 (DIT3), nothing should be connected to PORT9 (DSP3). Please set JP21 (OMCLK) to the "DIT" when MCLK is supplied to the AK4122. When MCLK frequency is changed, the value of X'tal (X2) frequency should be changed according to MCLK frequency. JP19 BICK JP20 LRCK JP21 OMCLK JP25 TST
DIT
EXT
DIT
EXT
DIT
EXT
OMCK
TST
* SW4 setting (See Table 19, 20, 21) Upper-side is "H" and lower-side is "L". SW4 No. 1 2 Name OCKS DIF0 ON ("H") OFF ("L") AK4114 Master Clock Output Setting Refer to Table 20 AK4114 Audio Format Setting Refer to Table 21 Table 19. SW4 setting
Mode 0 1
OCKS 0 1
MCKO1 X'tal fs 256fs 256fs 96kHz 512fs 512fs 48kHz Table 20. AK4114 MCKO1 setting
Default
Mode 0 1
AK4114 AK4122 DIF0 ODIF 24bit, MSB justified 0 0 Default 24bit, I2S Compatible 1 1 Table 21. AK4114 Audio interface format setting Audio I/F Format
* ODIF of the AK4122 is set by the register.
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2003/06
ASAHI KASEI
[AKD4122]
2. When connecting with the serial interface of UPD, ROHDE & SCHWARZ When using PORT9 (DSP3), nothing should be connected to PORT10 (DIT3). MCLK is input from J3 (EXT3), BICK and LRCK are supplied by using the clock dividing circuit on this evaluation board to the AK4122. Set JP21 (OMCLK) to the "EXT" when MCLK is supplied to the AK4122. JP19 BICK JP20 LRCK JP21 OMCLK JP25 TST
DIT
EXT
DIT
EXT
DIT
EXT
OMCK
TST
* Clock Setting MCLK is input from J3 (EXT3), BICK and LRCK are generated by using the clock dividing circuit. JP8 (DIV3) and JP9 (CLK3) are set by referring to Table 22. JP10 (EXT3) should be open. JP8 DIV3 JP9 CLK3 JP10 EXT3
256 256 512 768
384
fs 32kHz
44.1kHz
48kHz
88.2kHz 96kHz
MCLK JP8(DIV3) JP9(CLK3) 256fs = 8.192MHz 256 256 384fs = 12.288MHz Open 384 512fs = 16.384MHz 512 256 768fs = 24.576MHz 768 256 256fs = 11.2896MHz 256 256 384fs = 16.9344MHz Open 384 512fs = 22.5792MHz 512 256 768fs = 33.8688MHz 768 256 256fs = 12.288MHz 256 256 384fs = 18.432MHz Open 384 512fs = 24.576MHz 512 256 768fs = 36.864MHz 768 256 256fs = 22.5792MHz 256 256 384fs = 33.8688MHz Open 384 256fs = 24.576MHz 256 256 384fs = 36.864MHz Open 384 Table 22. Example for Clock setting
3. All clocks are fed through the 10pin port When using PORT9 (DSP3), nothing should be connected to PORT10 (DIT3). Set JP25 (TST) to the "OMCK" when MCLK is supplied to the AK4122. JP10 (EXT3) should be short. JP19 BICK JP20 LRCK JP21 OMCLK JP25 TST
DIT
EXT
DIT
EXT
DIT
EXT
OMCK
TST
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2003/06
ASAHI KASEI
[AKD4122]
(5-2) Master mode MCLK must be provided in the master mode. 1. When using DIT function of AK4114 (U14) When using X'tal (X2) and PORT10 (DIT3), nothing should be connected to PORT9 (DSP3). Set JP21 (OMCLK) to the "DIT" in order to supply MCLK to the AK4122. When MCLK frequency is changed, the value of X'tal (X2) frequency should be changed according to MCLK frequency. JP19 BICK JP20 LRCK JP21 OMCLK JP25 TST
DIT
EXT
DIT
EXT
DIT
EXT
OMCK
TST
* SW4 setting (See Table 23, 24, 25) Upper-side is "H" and lower-side is "L". SW4 No. 1 2 Name OCKS DIF0 ON ("H") OFF ("L") AK4114 Master Clock Output Setting Refer to Table 24 AK4114 Audio Format Setting Refer to Table 25 Table 23. SW4 setting
Mode 0 1
OCKS MCKO1 X'tal fs 0 256fs 256fs 96kHz 1 512fs 512fs 48kHz Table 24. AK4114 MCKO1 setting Audio I/F Format
Mode
AK4114 AK4122 DIF0 ODIF 0 24bit, MSB justified 0 0 1 24bit, I2S Compatible 1 1 Table 25. AK4114 Audio interface format setting
* ODIF of the AK4122 is set by the register.
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2003/06
ASAHI KASEI
[AKD4122]
2. When connecting with the serial interface of UPD, ROHDE & SCHWARZ When using PORT9 (DSP3), nothing should be connected to PORT10 (DIT3). MCLK is input from J3 (EXT3), BICK LRCK, and DATA are supplied from the AK4122. Set JP21 (OMCLK) to the "EXT" in order to supply MCLK to the AK4122. JP19 BICK JP20 LRCK JP21 OMCLK JP25 TST
DIT
EXT
DIT
EXT
DIT
EXT
OMCK
TST
* Clock Setting MCLK is input from J3 (EXT3). JP10 (EXT3) should be open. JP8 DIV3 JP9 CLK3 JP10 EXT3
256 256 512 768
384
3. All clocks are fed through the 10pin port When using PORT9 (DSP3), nothing should be connected to J3 (EXT3) and PORT10 (DIT3). Set JP25 (TST) to the "OMCK" in order to supply MCLK to the AK4122. JP10 (EXT3) should be short. MCLK is supplied to the AK4122, and BICK, LRCK and DATA are supplied from the AK4122. JP19 BICK JP20 LRCK JP21 OMCLK JP25 TST
DIT (5-3) SW1 setting
EXT
DIT
EXT
DIT
EXT
OMCK
TST
Set SW1 according to the mode of the AK4122 PORT3. SW1 No. 1 2 3 Name M/S2 M/S3 TST4 ON ("H") OFF ("L") Master Mode Slave Mode Master Mode Slave Mode Fixed to "L" Table 26. SW1 setting Default L L L
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ASAHI KASEI
[AKD4122]
n Other jumper pins set up
1. JP1 (GND) : Analog ground and Digital ground OPEN: Separated. SHORT: Common. (The connector "DGND" can be open.) 2. JP22 (VDD2) : DVDD and VCC OPEN: Separated. SHORT: Common. (The connector "VCC" can be open.) 3. JP23 (VDD1) : AVDD and DVDD OPEN: Separated. SHORT: Common. (The connector "DVDD" can be open.) 4. JP24 (REG) : +5V and AVDD OPEN: Separated. SHORT: Common. (The connector "AVDD" can be open.) The regulator can be supplied 3.3V to all circuits by shorting JP22, 23 and 24 and supplying 5V to +5V connector.
n The function of the toggle SW
Upper-side is "H" and lower-side is "L". [SW5] (SMUTE): Soft mute of AK4122 [SW6] (PDN): Resets the AK4122. Keep "H" during normal operation. The AK4122 should be resets once bringing "L" upon power-up. [SW7] (PDN1): Resets the AK4114 (U12). Keep "H" during normal operation. The AK4114 (U12) should be resets once bringing "L" upon power-up. Keep "L" when AK4114 (U12) is not used. [SW8] (PDN2): Resets the AK4114 (U13). Keep "H" during normal operation. The AK4114 (U13) should be resets once bringing "L" upon power-up. Keep "L" when AK4114 (U13) is not used. [SW9] (PDN3): Resets the AK4114 (U14). Keep "H" during normal operation. The AK4114 (U14) should be resets once bringing "L" upon power-up. Keep "L" when AK4114 (U14) is not used.
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2003/06
ASAHI KASEI
[AKD4122]
n Indication for LED
[LED1] (ERF): Monitor INT0 pin of the AK4114 (U12). LED turns on when unlock or parity error occurs. [LED2] (ERF): Monitor INT0 pin of the AK4114 (U13). LED turns on when unlock or parity error occurs. [LED3] (INT0): Monitor INT0 pin of the AK4122. [LED4] (INT1): Monitor INT1 pin of the AK4122. [LED5] (INT2): Monitor INT2 pin of the AK4122.
n Serial Control
The AK4122 can be controlled via the printer port (parallel port) of IBM-AT compatible PC. Connect PORT1 (CTRL) with PC by 10 wire flat cable packed with the AKD4122.
Connect PC
CSN CCLK CDTI CDTO
AKD4122
10 wire flat cable
10pin Connector
10pin Header
Figure 12. Connection of 10 wire flat cable
- 20 -
2003/06
ASAHI KASEI
[AKD4122]
2. Control Software Manual n Set-up of evaluation board and control software
1. Set up the AKD4122 according to previous term. 2. Connect IBM-AT compatible PC with AKD4122 by 10-line type flat cable (packed with AKD4122). Take care of the direction of 10pin header. (Please install the driver in the CD-ROM when this control software is used on Windows 2000/XP. Please refer "Installation Manual of Control Software Driver by AKM device control software". In case of Windows95/98/ME, this installation is not needed. This control software does not operate on Windows NT.) 3. Insert the CD-ROM labeled "AK4122 Evaluation Kit" into the CD-ROM drive. 4. Access the CD-ROM drive and double-click the icon of "AKD4122-1.exe" and "AKD4122-2"to set up the control program. 5. Then please evaluate according to the follows.
n Operation flow
Keep the following flow. 1. Set up the control program according to explanation above. 2. Click "Port Setup" button. 3. Click "Write default" button. Then set up the dialog and input data.
n Explanation of each buttons
1. [Port Setup] : 2. [Write default] : 3. [All Read] : 4. [Function1] : 5. [Write] : 6. [Read] : Set up the printer port. Initialize the register of AK4122. Read the all register of AK4122. Dialog to write data by keyboard operation. Dialog to write data by mouse operation. Read each register data by mouse operation.
n Explanation of each dialog
1. [Function1 Dialog] : Dialog to write data by keyboard operation Address Box: Data Box: Input register address in 2 figures of hexadecimal. Input register data in 2 figures of hexadecimal.
If you want to write the input data to AK4122, click "OK" button. If not, click "Cancel" button. 2. [Write Dialog] : Dialog to write data by mouse operation There are dialogs corresponding to each register. Click the "Write" button corresponding to each register to set up the dialog. If you check the check box, data becomes "H" or "1". If not, "L" or "0". If you want to write the input data to AK4122, click "OK" button. If not, click "Cancel" button.
- 21 -
2003/06
ASAHI KASEI
[AKD4122]
n Indication of data
Input data is indicated on the register map. Red letter indicates "H" or "1" and blue one indicates "L" or "0". Blank is the part that is not defined in the datasheet.
- 22 -
2003/06
ASAHI KASEI
[AKD4122]
MEASUREMENT RESULTS
[Measurement condition] * Measurement unit * Power Supply * Band width * Temperature * Measurement Path [Measurement Result] SRC Characteristics THD+N (Input = 1kHz, 0dBFS) FSO/FSI = 44.1kHz/48kHz FSO/FSI = 48kHz/44.1kHz FSO/FSI = 32kHz/48kHz FSO/FSI = 96kHz/32kHz Worst Case (FSO/FSI = 48kHz/8kHz) Dynamic Range (Input = 1kHz, -60dBFS) FSO/FSI = 44.1kHz/48kHz FSO/FSI = 48kHz/44.1kHz FSO/FSI = 32kHz/48kHz FSO/FSI = 96kHz/32kHz Worst Case (FSO/FSI = 32kHz/44.1kHz) Dynamic Range (Input = 1kHz, -60dBFS, A-weighted) FSO/FSI = 44.1kHz/48kHz Result 113.6 113.3 114.0 113.3 111.6 115.0 115.1 115.0 115.1 115.0 117.2 Unit dB dB dB dB dB dB dB dB dB dB dB
: Audio Precision, System Two Cascade : AVDD = DVDD = 3.3V : 10Hz FSO/2 : Room : AK4122 PORT1 SRC AK4122 PORT3
- 23 -
2003/06
ASAHI KASEI
[AKD4122]
[Plot]
AKM
-100 -102 -104 -106 -108 -110 -112 d B F S -114 -116 -118 -120 -122 -124 -126 -128 -130 -130
AK4122 THD+N vs. Input Level AVDD=DVDD=3.3V, FSI=44.1kHz, FSO=48kHz, fin=1kHz
-120
-110
-100
-90
-80
-70 dBFS
-60
-50
-40
-30
-20
-10
+0
Fig 1. THD+N vs. Input Level
AKM
-80
AK4122 THD+N vs. Input Frequency AVDD=DVDD=3.3V, FSI=44.1kHz, FSO=48kHz, Input=0dBFS
-85
-90
-95
-100 d B F S
-105
-110
-115
-120
-125
-130 20
50
100
200
500 Hz
1k
2k
5k
10k
20k
Fig 2. THD+N vs. Input Frequency (Input = 0dBFS)
- 24 -
2003/06
ASAHI KASEI
[AKD4122]
AKM
-80
AK4122 THD+N vs. Input Frequency AVDD=DVDD=3.3V, FSI=44.1kHz, FSO=48kHz, Input=-60dBFS
-85
-90
-95
-100 d B F S
-105
-110
-115
-120
-125
-130 20
50
100
200
500 Hz
1k
2k
5k
10k
20k
Fig 3. THD+N vs. Input Frequency (Input = -60dBFS)
AKM
+0 -10 -20 -30 -40 -50 d B F S -60 -70 -80 -90 -100 -110 -120 -130 -130
AK4122 Linearity AVDD=DVDD=3.3V, FSI=44.1kHz, FSO=48kHz, fin=1kHz
-120
-110
-100
-90
-80
-70 dBFS
-60
-50
-40
-30
-20
-10
+0
Fig 4. Linearity
- 25 -
2003/06
ASAHI KASEI
[AKD4122]
AKM
-0 -0.25 -0.5 -0.75 -1 -1.25 -1.5 d B F S -1.75 -2 -2.25 -2.5 -2.75 -3 -3.25 -3.5 -3.75 -4 2k 4k
AK4122 Frequency Response AVDD=DVDD=3.3V, FSI=44.1kHz, FSO=48kHz, Input=0dBFS
6k
8k
10k Hz
12k
14k
16k
18k
20k
22k
Fig 5. Frequency Response
AKM
+0 -10 -20 -30 -40 -50 -60 -70 d B F S -80 -90 -100 -110 -120 -130 -140 -150 -160 -170 -180 20 50 100 200 500 Hz 1k 2k 5k 10k 20k
AK4122 FFT Plot AVDD=DVDD=3.3V, FSI=44.1kHz, FSO=48kHz, Input=0dBFS, fin=1kHz
Fig 6. FFT Plot (Input = 0dBFS)
- 26 -
2003/06
ASAHI KASEI
[AKD4122]
AKM
+0 -10 -20 -30 -40 -50 -60 -70 d B F S -80 -90 -100 -110 -120 -130 -140 -150 -160 -170 -180 20 50
AK4122 FFT Plot AVDD=DVDD=3.3V, FSI=44.1kHz, FSO=48kHz, Input=-60dBFS, fin=1kHz
100
200
500 Hz
1k
2k
5k
10k
20k
Fig 7. FFT Plot (Input = -60dBFS)
IMPORTANT NOTICE * These products and their specifications are subject to change without notice. Before considering any use or application, consult the Asahi Kasei Microsystems Co., Ltd. (AKM) sales office or authorized distributor concerning their current status. * AKM assumes no liability for infringement of any patent, intellectual property, or other right in the application or use of any information contained herein. * Any export of these products, or devices or systems containing them, may require an export license or other official approval under the law and regulations of the country of export pertaining to customs and tariffs, currency exchange, or strategic materials. * AKM products are neither intended nor authorized for use as critical components in any safety, life support, or other hazard related device or system, and AKM assumes no responsibility relating to any such use, except with the express written consent of the Representative Director of AKM. As used here: a. A hazard related device or system is one designed or intended for life support or maintenance of safety or for applications in medicine, aerospace, nuclear energy, or other fields, in which its failure to function or perform may reasonably be expected to result in loss of life or in significant injury or damage to person or property. b. A critical component is one whose failure to function or perform may reasonably be expected to result, whether directly or indirectly, in the loss of the safety or effectiveness of the device or system containing it, and which must therefore meet very high standards of performance and reliability. * It is the responsibility of the buyer or distributor of an AKM product who distributes, disposes of, or otherwise places the product with a third party to notify that party in advance of the above content and conditions, and the buyer or distributor agrees to assume any and all responsibility and liability for and hold AKM harmless from any and all claims arising from the use of said product in the absence of such notification. - 27 2003/06
A
B
C
D
E
VCC
DVDD OMCLK
SDTO
BICK
PORT1
E
1 2 3 4 5
10 9 8 7 6
CSN CCLK CDTI CDTO
R4 R5 R6
470 470 470
U1
2 3 4 5 6 7 8 9 1 19 A1 A2 A3 A4 A5 A6 A7 A8 G1 G2 Y1 Y2 Y3 Y4 Y5 Y6 Y7 Y8 18 17 16 15 14 13 12 11
INT1
INT0
R1 47k
R2 47k
R3 47k
LRCK
VCC R7 51 R8 51 R9 51 R10 51 R11 51 R12 51 C1 0.1u
48 47 46 45 44 43 42 41 40 39 38 37
E
PORT2
3 2 1 IN VCC GND
CTRL
CN1
TX
74LVC541
C2 10u +
48 47 46 45 44
43
42
41
40
39
38
D
TX
INT1
OMCLK
R13 51
1 1 CDTI
DVDD
SDTO
BVSS
CCLK
DVSS
LRCK
BICK
CSN
INT0
CN2
U2
37
C3 0.1u
CN3 R14 51
SDTIO 36 36
D
SDTIO R16 51
R15 51
2 2 CDTO BICK2 35 35
BICK2 R17 51
TST1
3
3
TST1
LRCK2
34
34
LRCK2 R18 51
INT2 VCC M/S2 M/S3 TST4 SW1
1 2 3 4 5 6
4
4
INT2
MCLK2
33
33
MCLK2
5
5
TST2
DVDD
32
32
C
PORT3_DIF1
C4 0.1u +
6 6 TST3
C5 10u
31
C
AK4122 R68 R69 R70 47K 47K 47K
AK4122
DVSS
31
R19 51
SDTI 30 30
7
7
M/S2
SDTI R20 51
8
8
M/S3
BICK1
29
29
BICK1 R21 51
SMUTE
9
9
SMUTE
LRCK1
28
28
LRCK1
10
10
TST4
PDN
27
27
PDN
VCC
B
11
11
TST5
AVSS
26
26
L1 47u
12 12 FILT TST10 TST11 AVDD AVSS TST6 TST7 TST8 TST9 RX1 RX2 RX3 RX4 R 25 25
B
PORT3
VCC GND OUT 3 2 1
13
14
15
16
17
18
19
20
21
22
23
DIR R24 470
OPT JP3 JP2 RX
C8 2.2u
C9 0.1u C10 10u +
24
C6 0.1u
C7 2.2n
R23 470
R22 12k
JP1 GND
J1 RX
A
RX1 RX2 RX3 RX4
RX1 RX2 RX3 RX4 CN4
13
RX1-4 R25 75 C11 0.1u BNC
Analog Ground
14 15 16 17 18 19 20 21 22 23 24
Digital Ground
A
Title
RX3
AVDD
RX1
RX2
RX4
AKD4122
Document Number
Size
A3
Date:
C D
AK4122
Sheet
E
Rev
A 1
of
Tuesday, January 07, 2003
6
A
B
A
B
C
D
E
VCC
A A
For AK4122 PORT2
10
4
U4A 74AC74
Q 5
U3
1 1G 1A 2G 1Y 2A 3G 3A 3Y 4G 4A 4Y 11 2Y 6 8 VCC GND 14 7 3
VCC
U4B 74AC74
Q 9
CL
J2 EXT2
PR
12 11
D CLK
256 512 768
JP4
3
D CLK
PR
2
256 JP5 CLK2 384 U5
10 11 CLK RST Q1 Q2 Q3 Q4 Q5 Q6 Q7 Q8 Q9 Q10 Q11 Q12 9 7 6 5 3 2 4 13 12 14 15 1
2
C12 0.1u EXT_MCLK2 EXT_BICK2 EXT_LRCK2
64fs 32fs fs
JP6 BCFS
4 5 10 9 13 12
Q
6
CL
JP7 EXT2
B
13
R26 51
Q
8
1
DIV2
U6
3 4 5 6 7 10 2 9 1 A B C D ENP ENT CLK LOAD CLR QA QB QC QD RCO 14 13 12 11 15
74HC4040
74VHC125
B
74AC163
2
1
U16A 74HC14
C C
VCC
U8
4
VCC
VCC GND 1Y 14 7 3 6 8 11
U9A 74AC74
Q 5
1 2
1G 1A 2G 2A 3G 3A
10
CL
J3 EXT3
D CLK
PR
12 11
Q
9
256 512 768
JP8
3
D CLK
PR
For AK4122 PORT3
U9B 74AC74
2
256
4
C13 0.1u EXT_MCLK3 EXT_BICK3 EXT_LRCK3
D
Q
6
JP9 CLK3 384
U10
10 11 CLK RST Q1 Q2 Q3 Q4 Q5 Q6 Q7 Q8 Q9 Q10 Q11 Q12 9 7 6 5 3 2 4 13 12 14 15 1
64fs
5 10 9
CL
D
13
R27 51 JP10 EXT3
Q
8
1
DIV3
2Y 3Y
fs
13 12
4G 4A 4Y
74VHC125
U11
3 4 5 6 7 10 2 9 1 A B C D ENP ENT CLK LOAD CLR QA QB QC QD RCO 14 13 12 11 15
74HC4040
74AC163
E E
4
3
U16B 74HC14
Title Size Document Number
AKD4122
External Clock
Sheet
E
Rev
A3
Date:
A B C D
A
of
Tuesday, January 07, 2003
2
6
A
B
C
D
E
VCC VCC
E E
2
PORT4
VCC GND OUT 3 2 1
L2 47u + C15 0.1u
1
D3 HSU119
R63 10k
11 10 9 8
4114_PDN1
L 3 1
H
R28 470
C16 0.1u R29 18k
D
C17 0.47u
D
48
47
46
45
44
43
42
41
40
39
38
U12
TEST1
AVSS
VCOM
AVDD
INT1
RX3
RX2
RX1
RX0
NC
NC
R
37
U7C
INT0 36 5 6
R30 1k
2
LED1 ERF
1
2
DIR1
C14 10u
SW7 PDN1
C61 0.1u
U7E 74HC14
U7D 74HC14
1
IPS0
2
NC
PORT1_DIF0
3
DIF0
4
TEST2
C
PORT1_DIF1
5
DIF1
6
NC
AK4114
PORT1_DIF2
7
DIF2
8
IPS1
9
P/SN
10
B
XTL0
11
XTL1
12
VIN MCKO1 COUT UOUT DVDD BOUT VOUT DVSS DVSS TVDD LRCK
TX0
TX1
13
14
15
16
17
18
19
20
21
22
23
24
C18 0.1u C20 10u +
+
A
A
B
+
74HC14
OCKS0 35
R31 100 BICK1 R32 100 PORT5 BICK1 LRCK1 SDTI
1 2 3 4 5 10 9 8 7 6
OCKS1
34
PORT1_OCKS1
LRCK1 R33 100
DSP1
CM1
33
SDTI R34 220k R35 220k R36 220k
C
CM0
32
PDN
31
4114_PDN1
XTI
30
XTO
29
EXT
DAUX 28
U7B 74HC14
4 3 2
U7A 74HC14
1
J4 EXT1
JP11 BICK1
MCKO2 27
R37 51 JP12 EXT1
DIR
26
B
BICK
JP13 SDTO
SDTO 25
VCC OCKS DIF0 DIF1 DIF2 SW2
1 2 3 4 8 7 6 5
C19 0.1u C21 10u
JP14 LRCK1 R71 R72 R73 R74 U7F 47K 47K 47K 47K
PORT1 PORT1_OCKS1 PORT1_DIF0 PORT1_DIF1 PORT1_DIF2
A
13
12
74HC14
Title Size Document Number
AKD4122
PORT1
Sheet
E
Rev
A3
Date:
C D
A 3
of
Tuesday, January 07, 2003
6
A
B
C
D
E
VCC
VCC
E E
PORT6
VCC GND OUT 3 2 1
L3 47u C23 0.1u R38 470
2
DIR2
1
C22 10u C24 0.1u
3
1
+ D4 HSU119 R64 10k
11 L H 10 9 8
4114_PDN2
C25 0.47u
39
48
47
46
45
44
43
42
41
40
38
U13
D
TEST1
AVSS
VCOM
AVDD
INT1
RX3
RX2
RX1
RX0
NC
NC
R
37
2
R39 18k
SW8 PDN2
C62 0.1u
U16E 74HC14
U16D 74HC14
1
IPS0
2
NC
PORT2_DIF0
3
DIF0
4
TEST2
PORT2_DIF1
5
DIF1
C
6
NC
AK4114
PORT2_DIF2
1
7
DIF2
8
2
IPS1
9
P/SN
10
XTL0
11
XTL1
B
12
VIN MCKO1 COUT UOUT DVDD BOUT VOUT DVSS DVSS TVDD LRCK
TX0
TX1
13
14
15
16
17
18
19
20
21
22
23
C28 0.1u C30 10u +
C29 0.1u C31 10u +
24
PORT8
IN VCC GND
A
3 2 1
DIT2
C32 0.1u U16F 74HC14
13 12
A
B
+
U16C 74HC14
INT0 36 5 6
R40 1k
2
LED2 ERF
1
D
OCKS0
35
R41 100
34
OCKS1
PORT2_OCKS1
MCLK2 R42 100
CM1
33
BICK2 R43 100 LRCK2 MCLK2 BICK2 LRCK2 SDTIO PORT7
1 2 3 4 5 10 9 8 7 6
CM0
32
PDN
31
4114_PDN2 C26 (open) SDTIO R45 220k R46 220k R47 220k
R44 100
DSP2
C
XTI
30
X1 11.2896MHz
XTO 29
R48 220k
C27 (open)
DAUX 28
MCKO2
27
JP15 SDTIO DIR JP16 BICK2 EXT EXT_BICK2 R75 R76 R77 R78 47K 47K 47K 47K OCKS DIF0 DIF1 DIF2 SW3
1 2 3 4 8 7 6 5
VCC
BICK
26
B
SDTO
25
PORT2 PORT2_OCKS1 PORT2_DIF0 PORT2_DIF1 PORT2_DIF2
DIR JP17 LRCK2 EXT DIR JP18 MCLK2 EXT_LRCK2
A
EXT
EXT_MCLK2
Title Size Document Number
AKD4122
PORT2
Sheet
E
Rev
A3
Date:
C D
A 4
of
Tuesday, January 07, 2003
6
A
B
C
D
E
VCC
E
VCC + C33 10u C34 0.1u
2 1
E
D5 HSU119
R65 10k
1 2 3 4
4114_PDN3
L 3 1
H
48
47
46
45
44
43
42
41
40
39
38
U14
D
37
2
C35 0.47u
R49 18k
SW9 PDN3
C63 0.1u
U15A 74HC14
U15B 74HC14
TEST1
AVSS
VCOM
AVDD
INT1
RX3
RX2
RX1
RX0
NC
NC
R
1
IPS0
2
NC
PORT3_DIF0
3
DIF0
4
TEST2
PORT3_DIF1
5
DIF1
C
6
NC
AK4114
1
7
DIF2
8
2
IPS1
9
P/SN
10
XTL0
11
XTL1
B
12
VIN MCKO1 COUT UOUT DVDD BOUT VOUT DVSS DVSS TVDD LRCK
TX0
TX1
13
14
15
16
17
18
19
20
21
22
23
C38 0.1u C40 10u +
C39 0.1u C41 10u +
24
PORT10
IN VCC GND
A
3 2 1
DIT3
C42 0.1u
A
B
+
TST1 TST
INT0 36
D
JP25 TST OMCK
OCKS0
35
R50 100
34
OCKS1
PORT3_OCKS1
OMCLK R51 100
CM1
33
BICK R52 100 LRCK OMCLK BICK LRCK SDTO PORT9
1 2 3 4 5 10 9 8 7 6
CM0
32
PDN
31
4114_PDN3 C36 (open) SDTO R54 220k R55 220k R56 220k
R53 100
DSP3
C
XTI
30
X2 24.576MHz
XTO 29
R57 220k
C37 (open)
DAUX 28
MCKO2
27
BICK
26
DIT JP19 BICK EXT EXT_BICK3 R66 R67 47K 47K VCC
4 3
B
SDTO
25
OCKS 1 DIF0 2
SW4
PORT3 PORT3_OCKS1 PORT3_DIF0
DIT JP20 LRCK EXT DIT JP21 OMCLK EXT_LRCK3
A
EXT
EXT_MCLK3
Title Size Document Number
AKD4122
PORT3
Sheet
E
Rev
A3
Date:
C D
A 5
of
Tuesday, January 07, 2003
6
A
B
C
D
E
A
VCC
A
2
1
D1 HSU119
R58 10k
5 6 9 8
SMUTE VCC
L 3 1
H
SW5 SMUTE
2
C43 0.1u
U15C 74HC14
U15D 74HC14
LED3 INT0
1 2
R59 1k
2 1
INT0
B
B
U17A 74HC14 LED4 INT1
1 2
R60 1k
4 3
INT1
VCC LED5 INT2
2 1 2
U17B 74HC14 R62 1k
6 5
1
D2 HSU119
R61 10k
13 12 11 10
INT2
U17C 74HC14 PDN
L 3 1
H
C
SW6 PDN
2
C44 0.1u
U15F 74HC14
U15E 74HC14
C
VCC
D
DVDD
AVDD
+5V
9
U17D 74HC14
8
D
For 74HC14 x 4, 74HC4040 x 2, 74AC74 x 2, 74AC163 x 2, 74LVC541 x 1
JP22 VDD2
L4 (short)
JP23 VDD1
L5 (short)
JP24 REG
T1 TA48M33F
OUT GND IN
U17E 74HC14
11 10
U17F 74HC14 C46 C47 0.1u 47u +
13 12
DVDD C64 0.1u C48 0.1u C49 0.1u C50 0.1u C51 0.1u C52 0.1u C53 0.1u C54 0.1u C55 0.1u C56 0.1u C57 0.1u C58 47u + C59 47u +
AVDD C60 + 47u
C45 0.1u
E
E
Title Size Document Number
AKD4122
Power Supply
Sheet
E
A3
Date:
A B C D
Rev A of
Tuesday, January 07, 2003
6
6

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